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Espressif Systems /ESP32-P4 /PARL_IO /TX_CLK_CFG

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Interpret as TX_CLK_CFG

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TX_CLK_I_INV)TX_CLK_I_INV 0 (TX_CLK_O_INV)TX_CLK_O_INV

Description

Parallel IO TX clk configuration register

Fields

TX_CLK_I_INV

Set this bit to invert the input Tx core clock.
TX_CLK_O_INV

Set this bit to invert the output Tx core clock.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data